Dariaceli's Git
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Power saving changes, add new fonts, bitmaps and screens

Nils Faerber authored on 19/05/2013 00:07:04
Showing 1 changed files
metawatch/hal_devboard_v2_defs.h
History View file @ 1b57900
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@@ -328,6 +328,10 @@
328 328 
 // disable charging, sleep the part
329 329 
 #define BATTERY_CHARGE_DISABLE()  { BAT_CHARGE_OUT |= BAT_CHARGE_ENABLE_PIN; }
330 330
331 
+//RESET PIN NMI or RESET
332 
+#define SET_RESET_PIN_NMI() {SFRRPCR &= ~SYSRSTRE; SFRRPCR |= SYSNMI;}
333 
+#define SET_RESET_PIN_RST() {SFRRPCR |= SYSRSTRE; SFRRPCR &= ~SYSNMI;}
334 
+#define RESET_PIN (SFRRPCR & SYSNMI) // return 1 for NMI
331 335
332 336 
 //
333 337 
 // Ambient Light Sensor
Browse code

Here we are! MetaWatch support in Oswald!

Nils Faerber authored on 27/04/2013 20:22:32
Showing 1 changed files
metawatch/hal_devboard_v2_defs.h
History View file @ 1553c23
1 1 
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@@ -0,0 +1,660 @@
1 
+//==============================================================================
2 
+//  Copyright 2011 Meta Watch Ltd. - http://www.MetaWatch.org/
3 
+//
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+//  Licensed under the Meta Watch License, Version 1.0 (the "License");
5 
+//  you may not use this file except in compliance with the License.
6 
+//  You may obtain a copy of the License at
7 
+//
8 
+//      http://www.MetaWatch.org/licenses/license-1.0.html
9 
+//
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+//  Unless required by applicable law or agreed to in writing, software
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+//  distributed under the License is distributed on an "AS IS" BASIS,
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+//  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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+//  See the License for the specific language governing permissions and
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+//  limitations under the License.
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+//==============================================================================
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+
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+/******************************************************************************/
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+/*! \file hal_devboard_v2_defs.h
19 
+ *
20 
+ * Pin and peripheral definitions for Development Board Version 2
21 
+ */
22 
+/******************************************************************************/
23 
+
24 
+
25 
+#ifndef HAL_DEVBOARD_V2_DEFS_H
26 
+#define HAL_DEVBOARD_V2_DEFS_H
27 
+
28 
+
29 
+// Defines for the LCD display interface, single channel SPI output
30 
+#define LCD_5V_PDIR P4DIR
31 
+#define LCD_5V_POUT P4OUT
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+#define LCD_5V_BIT  BIT0
33 
+
34 
+#define ENABLE_LCD_POWER() { \
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+  LCD_5V_PDIR |= LCD_5V_BIT; \
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+  LCD_5V_POUT |= LCD_5V_BIT; \
37 
+}
38 
+
39 
+#define DISABLE_LCD_POWER() { \
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+  LCD_5V_PDIR |= LCD_5V_BIT; \
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+  LCD_5V_POUT &= ~LCD_5V_BIT; \
42 
+}
43 
+
44 
+#define LCD_ENABLE_PDIR ( P3DIR )
45 
+#define LCD_ENABLE_POUT ( P3OUT )
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+#define LCD_ENABLE_PIN  ( BIT6 )
47 
+
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+#define ENABLE_LCD_ENABLE() { \
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+  LCD_ENABLE_PDIR |= LCD_ENABLE_PIN; \
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+  LCD_ENABLE_POUT |= LCD_ENABLE_PIN; \
51 
+}
52 
+
53 
+#define DISABLE_LCD_ENABLE() { \
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+  LCD_ENABLE_PDIR |= LCD_ENABLE_PIN; \
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+  LCD_ENABLE_POUT &= ~LCD_ENABLE_PIN; \
56 
+}
57 
+
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+#define LCD_CS_PDIR ( P9DIR )
59 
+#define LCD_CS_POUT ( P9OUT )
60 
+#define LCD_CS_PIN  ( BIT0 )
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+
62 
+#define LCD_SPI_PORT_SEL ( P3SEL )
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+#define LCD_SPI_SIMO_BIT ( BIT1 )
64 
+#define LCD_SPI_CLK_BIT  ( BIT3 )
65 
+#define LCD_SPI_SOMI_BIT ( BIT2 )
66 
+
67 
+#define LCD_CS_ASSERT()   { LCD_CS_POUT |= LCD_CS_PIN; }
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+#define LCD_CS_DEASSERT() { LCD_CS_POUT &= ~LCD_CS_PIN; }
69 
+
70 
+#define CONFIG_LCD_PINS() { \
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+  LCD_SPI_PORT_SEL |= LCD_SPI_SIMO_BIT; \
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+  LCD_SPI_PORT_SEL |= LCD_SPI_CLK_BIT;  \
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+  LCD_SPI_PORT_SEL |= LCD_SPI_SOMI_BIT; \
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+  ENABLE_LCD_ENABLE();                  \
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+  LCD_CS_PDIR |= LCD_CS_PIN;            \
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+  LCD_CS_DEASSERT();                    \
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+}
78 
+
79 
+// labeled EL_EN on schematic
80 
+#define LCD_LED_PDIR ( P4DIR )
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+#define LCD_LED_POUT ( P4OUT )
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+#define LCD_LED_PIN  ( BIT4 )
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+
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+#define DISABLE_LCD_LED() { \
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+  LCD_LED_PDIR |= LCD_LED_PIN;  \
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+  LCD_LED_POUT &= ~LCD_LED_PIN; \
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+}
88 
+
89 
+#define ENABLE_LCD_LED() { \
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+  LCD_LED_PDIR |= LCD_LED_PIN;  \
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+  LCD_LED_POUT |= LCD_LED_PIN;  \
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+}
93 
+
94 
+#define LCD_SPI_UCBxCTL0            UCB0CTL0          // Control register
95 
+#define LCD_SPI_UCBxCTL1            UCB0CTL1          // Control register
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+#define LCD_SPI_UCBxBR0             UCB0BR0           // Baudrate prescale
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+#define LCD_SPI_UCBxBR1             UCB0BR1           // Baudrate divider
98 
+
99 
+#define LCD_SPI_UCBxTXBUF           UCB0TXBUF         // Transmit buffer
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+#define LCD_SPI_UCBxRXBUF           UCB0RXBUF         // Receive  buffer
101 
+
102 
+#define LCD_SPI_UCBxIE              UCB0IE            // Interrupt enable register
103 
+#define LCD_SPI_UCBxIFG             UCB0IFG           // Interrupt flag register
104 
+#define LCD_SPI_UCBxIV              UCB0IV            // Interrupt vector register
105 
+#define LCD_SPI_UCBxSTAT            UCB0STAT          // status register
106 
+
107 
+
108 
+// Definitions for the OLED Display
109 
+// peripheral mapping for OLED
110 
+#define OLED_I2C_CTL0  ( UCB0CTL0 )
111 
+#define OLED_I2C_CTL1  ( UCB0CTL1 )
112 
+#define OLED_I2C_BR0   ( UCB0BR0 )
113 
+#define OLED_I2C_BR1   ( UCB0BR1 )
114 
+#define OLED_I2C_I2CSA ( UCB0I2CSA )
115 
+#define OLED_I2C_IE    ( UCB0IE )
116 
+#define OLED_I2C_IFG   ( UCB0IFG )
117 
+#define OLED_I2C_TXBUF ( UCB0TXBUF )
118 
+#define OLED_I2C_RXBUF ( UCB0RXBUF )
119 
+// interrupt mapping for OLED
120 
+#define USCI_OLED_I2C_VECTOR ( USCI_B0_VECTOR )
121 
+#define USCI_OLED_I2C_IV     ( UCB0IV )
122 
+
123 
+// OLED reset is active low
124 
+#define OLED_RSTN_PDIR  ( P8DIR )
125 
+#define OLED_RSTN_POUT  ( P8OUT )
126 
+#define OLED_RSTN_PIN   ( BIT7  )
127 
+
128 
+#define OLED_RSTN_CONFIG()   { OLED_RSTN_PDIR |= OLED_RSTN_PIN; OLED_RSTN_ASSERT(); }
129 
+#define OLED_RSTN_ASSERT()   { OLED_RSTN_POUT &= ~OLED_RSTN_PIN; }
130 
+#define OLED_RSTN_DEASSERT() { OLED_RSTN_POUT |= OLED_RSTN_PIN; }
131 
+
132 
+#define OLED_CS1N_PDIR ( P8DIR )
133 
+#define OLED_CS1N_POUT ( P8OUT )
134 
+#define OLED_CS1N_PIN  ( BIT0 )
135 
+
136 
+#define OLED_CS1N_CONFIG()  { OLED_CS1N_PDIR |= OLED_CS1N_PIN; OLED_CS1N_DISABLE(); }
137 
+#define OLED_CS1N_ENABLE()  { OLED_CS1N_POUT &= ~OLED_CS1N_PIN; }
138 
+#define OLED_CS1N_DISABLE() { OLED_CS1N_POUT |= OLED_CS1N_PIN; }
139 
+
140 
+#define OLED_CS2N_PDIR ( P8DIR )
141 
+#define OLED_CS2N_POUT ( P8OUT )
142 
+#define OLED_CS2N_PIN  ( BIT1 )
143 
+
144 
+#define OLED_CS2N_CONFIG()  { OLED_CS2N_PDIR |= OLED_CS2N_PIN; OLED_CS2N_DISABLE(); }
145 
+#define OLED_CS2N_ENABLE()  { OLED_CS2N_POUT &= ~OLED_CS2N_PIN; }
146 
+#define OLED_CS2N_DISABLE() { OLED_CS2N_POUT |= OLED_CS2N_PIN; }
147 
+
148 
+#define OLED_SDA_PDIR ( P3DIR )
149 
+#define OLED_SDA_POUT ( P3OUT )
150 
+#define OLED_SDA_PIN  ( BIT1 )
151 
+#define OLED_SDA_PSEL ( P3SEL)
152 
+
153 
+#define OLED_SCL_PDIR ( P3DIR )
154 
+#define OLED_SCL_POUT ( P3OUT )
155 
+#define OLED_SCL_PORT ( P3 )
156 
+#define OLED_SCL_PIN  ( BIT2 )
157 
+#define OLED_SCL_PSEL ( P3SEL )
158 
+
159 
+// the select line overrides the pdir and pout settings
160 
+#define OLED_SDA_CONFIG_FOR_PERIPHERAL_USE() { OLED_SDA_PSEL |= OLED_SDA_PIN; }
161 
+#define OLED_SCL_CONFIG_FOR_PERIPHERAL_USE() { OLED_SCL_PSEL |= OLED_SCL_PIN; }
162 
+
163 
+#define OLED_I2C_CONFIG_FOR_PERIPHERAL_USE() { \
164 
+  OLED_SDA_CONFIG_FOR_PERIPHERAL_USE();        \
165 
+  OLED_SCL_CONFIG_FOR_PERIPHERAL_USE(); }
166 
+
167 
+#define OLED_SDA_CONFIG_FOR_SLEEP() { \
168 
+  OLED_SDA_PSEL &= ~OLED_SDA_PIN;     \
169 
+  OLED_SDA_PDIR |= OLED_SDA_PIN;      \
170 
+  OLED_SDA_POUT |= OLED_SDA_PIN; }
171 
+
172 
+#define OLED_SCL_CONFIG_FOR_SLEEP() { \
173 
+  OLED_SCL_PSEL &= ~OLED_SCL_PIN;     \
174 
+  OLED_SCL_PDIR |= OLED_SCL_PIN;      \
175 
+  OLED_SCL_POUT |= OLED_SCL_PIN; }
176 
+
177 
+#define OLED_I2C_CONFIG_FOR_SLEEP() { \
178 
+  OLED_SDA_CONFIG_FOR_SLEEP();        \
179 
+  OLED_SCL_CONFIG_FOR_SLEEP(); }
180 
+
181 
+#define OLED_POWER_ENABLE_PIN  ( BIT0 )
182 
+#define OLED_POWER_ENABLE_POUT ( P4OUT )
183 
+#define OLED_POWER_ENABLE_PDIR ( P4DIR )
184 
+#define OLED_POWER_CONFIG()    { P4DIR |= OLED_POWER_ENABLE_PIN; OLED_POWER_DISABLE(); }
185 
+#define OLED_POWER_ENABLE()    { P4OUT |= OLED_POWER_ENABLE_PIN; }
186 
+#define OLED_POWER_DISABLE()   { P4OUT &= ~OLED_POWER_ENABLE_PIN; }
187 
+
188 
+// VLED_EN is active low
189 
+#define OLED_IO_POWER_ENABLE_PIN  ( BIT3 )
190 
+#define OLED_IO_POWER_ENABLE_POUT ( P5OUT )
191 
+#define OLED_IO_POWER_ENABLE_PDIR ( P5DIR )
192 
+#define OLED_IO_POWER_CONFIG()    { P5DIR |= OLED_IO_POWER_ENABLE_PIN; OLED_IO_POWER_DISABLE(); }
193 
+#define OLED_IO_POWER_ENABLE()    { P5OUT &= ~OLED_IO_POWER_ENABLE_PIN; }
194 
+#define OLED_IO_POWER_DISABLE()   { P5OUT |= OLED_IO_POWER_ENABLE_PIN; }
195 
+
196 
+#ifdef ANALOG
197 
+#define CONFIG_OLED_PINS() {   \
198 
+  OLED_RSTN_CONFIG();          \
199 
+  OLED_CS1N_CONFIG();          \
200 
+  OLED_CS2N_CONFIG();          \
201 
+  OLED_POWER_CONFIG();         \
202 
+  OLED_I2C_CONFIG_FOR_SLEEP(); \
203 
+  OLED_IO_POWER_CONFIG();      \
204 
+}
205 
+#else
206 
+/* jumpers for 10V must be removed for power consumption measurements */
207 
+#define CONFIG_OLED_PINS() {       \
208 
+  OLED_RSTN_CONFIG();              \
209 
+  OLED_CS1N_CONFIG();              \
210 
+  OLED_CS1N_ENABLE();              \
211 
+  OLED_CS2N_CONFIG();              \
212 
+  OLED_CS2N_ENABLE();              \
213 
+  OLED_POWER_CONFIG();             \
214 
+  OLED_IO_POWER_CONFIG();          \
215 
+}
216 
+#endif
217 
+
218 
+
219 
+// Real time clock defines
220 
+// RTC 1 Hz output, also used to toggle the bias on the LCD
221 
+#define RTC_1HZ_PORT_DIR  ( P2DIR )
222 
+#define RTC_1HZ_PORT_SEL  ( P2SEL )
223 
+#define RTC_1HZ_BIT       ( BIT4 )
224 
+
225 
+
226 
+// Button defines
227 
+
228 
+#define BUTTON_TIME_COUNT_ARRAY_LEN  8
229 
+#define ALL_BUTTONS_OFF              0xFF
230 
+
231 
+#define SW_A  BIT0
232 
+#define SW_B  BIT1
233 
+#define SW_C  BIT2
234 
+#define SW_D  BIT3
235 
+// Bit 4 is not used
236 
+#define SW_E  BIT5
237 
+#define SW_F  BIT6
238 
+#define SW_P  BIT7
239 
+
240 
+#define SW_A_INDEX        ( 0 )
241 
+#define SW_B_INDEX        ( 1 )
242 
+#define SW_C_INDEX        ( 2 )
243 
+#define SW_D_INDEX        ( 3 )
244 
+#define SW_UNUSED_INDEX   ( 4 )
245 
+#define SW_E_INDEX        ( 5 )
246 
+#define SW_F_INDEX        ( 6 )
247 
+#define SW_P_INDEX        ( 7 )
248 
+#define TOTAL_BTN_NUM     ( 8 )
249 
+
250 
+#ifdef ANALOG
251 
+  /* analog board has traces for all of the buttons but
252 
+   * only 3 and pull switch are populated */
253 
+  #define ALL_BUTTONS (SW_A | SW_B | SW_C | SW_P)
254 
+
255 
+#elif defined(DIGITAL)
256 
+
257 
+  #define ALL_BUTTONS (SW_A | SW_B | SW_C | SW_D | SW_E | SW_F)
258 
+
259 
+#endif
260 
+
261 
+#define RESISTOR_ENABLE_BUTTONS ( ALL_BUTTONS )
262 
+#define INT_EDGE_SEL_BUTTONS     (ALL_BUTTONS)
263 
+
264 
+#define BUTTON_PORT_VECTOR PORT2_VECTOR
265 
+#define BUTTON_PORT_DIR    P2DIR
266 
+#define BUTTON_PORT_SEL    P2SEL
267 
+#define BUTTON_PORT_OUT    P2OUT
268 
+#define BUTTON_PORT_REN    P2REN
269 
+#define BUTTON_PORT_IE     P2IE
270 
+#define BUTTON_PORT_IES    P2IES
271 
+#define BUTTON_PORT_IFG    P2IFG
272 
+
273 
+#define DISABLE_BUTTONS() { \
274 
+  BUTTON_PORT_IE  &= ~INT_EDGE_SEL_BUTTONS; \
275 
+  BUTTON_PORT_REN &= ~ALL_BUTTONS;          \
276 
+  BUTTON_PORT_OUT &= ~ALL_BUTTONS;          \
277 
+}
278 
+
279 
+/* SHIPPING */
280 
+/* S5 or SW_E is the button that takes the watch out of shipping mode */
281 
+#define ENABLE_SHIPPING_WAKEUP() { \
282 
+  P1IE = 0x00;                              \
283 
+  PMMCTL0_H = 0xA5;                         \
284 
+  PMMRIE = 0x0000;                          \
285 
+  RTCPS0CTL = 0x0000;                       \
286 
+  RTCPS1CTL = 0x0000;                       \
287 
+  UCSCTL8 = 0x0700;                         \
288 
+  BUTTON_PORT_REN = SW_E;                   \
289 
+  BUTTON_PORT_OUT = SW_E;                   \
290 
+  BUTTON_PORT_DIR &= ~SW_E;                 \
291 
+  BUTTON_PORT_IES  =   SW_E;                \
292 
+  BUTTON_PORT_IFG  =   0x00;                \
293 
+  BUTTON_PORT_IE   =   SW_E;                \
294 
+}
295 
+
296 
+// NOTE the the buttons are grounded. That means that we want to invert the bits
297 
+// when reading the port to have positive logic where a button press is a "1"
298 
+#define BUTTON_PORT_IN     ~P2IN
299 
+
300 
+// Configure the hardware port for the button support P2.4 is excluded
301 
+#define CONFIGURE_BUTTON_PINS() { \
302 
+  BUTTON_PORT_REN = (unsigned char) RESISTOR_ENABLE_BUTTONS; \
303 
+  BUTTON_PORT_OUT = (unsigned char) ALL_BUTTONS;             \
304 
+  BUTTON_PORT_DIR &= (unsigned char) ~ALL_BUTTONS;           \
305 
+  BUTTON_PORT_IES |=   INT_EDGE_SEL_BUTTONS;         \
306 
+  BUTTON_PORT_IFG &=  ~ALL_BUTTONS;                  \
307 
+  BUTTON_PORT_IE  |=   ALL_BUTTONS;                  \
308 
+}
309 
+
310 
+
311 
+// Battery charger control for a BQ24080
312 
+#define BAT_CHARGE_DIR        P6DIR
313 
+#define BAT_CHARGE_REN        P6REN
314 
+#define BAT_CHARGE_OUT        P6OUT
315 
+#define BAT_CHARGE_IN         P6IN
316 
+//#define BAT_CHARGE_IE         P6IE
317 
+//#define PWR_PORT_VECTOR       PORT6_VECTOR
318 
+//#define PWR_PORT_IFG          P6IFG
319 
+
320 
+#define BAT_CHARGE_ENABLE_PIN  BIT2
321 
+#define BAT_CHARGE_STAT1       BIT3
322 
+#define BAT_CHARGE_STAT2       BIT4
323 
+#define BAT_CHARGE_PWR_BIT     BIT5
324 
+
325 
+// Enable charging, asserted low
326 
+#define BATTERY_CHARGE_ENABLE()   { BAT_CHARGE_OUT &= ~BAT_CHARGE_ENABLE_PIN; }
327 
+
328 
+// disable charging, sleep the part
329 
+#define BATTERY_CHARGE_DISABLE()  { BAT_CHARGE_OUT |= BAT_CHARGE_ENABLE_PIN; }
330 
+
331 
+
332 
+//
333 
+// Ambient Light Sensor
334 
+//
335 
+#define GC1_PDIR ( P6DIR )
336 
+#define GC1_POUT ( P6OUT )
337 
+#define GC1_PSEL ( P6SEL )
338 
+#define GC1_PIN  ( BIT0 )
339 
+
340 
+#define GC2_PDIR ( P6DIR )
341 
+#define GC2_POUT ( P6OUT )
342 
+#define GC2_PSEL ( P6SEL )
343 
+#define GC2_PIN  ( BIT6 )
344 
+
345 
+#define IOUT_PDIR ( P6DIR )
346 
+#define IOUT_PSEL ( P6SEL )
347 
+#define IOUT_PIN  ( BIT1 )
348 
+
349 
+#define LIGHT_SENSE_INIT()                     \
350 
+{                                              \
351 
+  IOUT_PDIR &= ~IOUT_PIN;                      \
352 
+  IOUT_PSEL |= IOUT_PIN;                       \
353 
+  GC1_PDIR  |= GC1_PIN;                        \
354 
+  GC2_PDIR  |= GC2_PIN;                        \
355 
+  LIGHT_SENSE_DISABLE();                       \
356 
+}
357 
+
358 
+#define LIGHT_SENSOR_SHUTDOWN() \
359 
+{                               \
360 
+  GC1_POUT &= ~GC1_PIN;         \
361 
+  GC2_POUT &= ~GC2_PIN;         \
362 
+}
363 
+
364 
+#define LIGHT_SENSOR_L_GAIN() \
365 
+{                             \
366 
+  GC1_POUT |= GC1_PIN;        \
367 
+  GC2_POUT |= GC2_PIN;        \
368 
+}
369 
+
370 
+#define LIGHT_SENSE_ENABLE()\
371 
+{                           \
372 
+  LIGHT_SENSOR_L_GAIN();    \
373 
+}
374 
+
375 
+#define LIGHT_SENSE_DISABLE() \
376 
+{                             \
377 
+  LIGHT_SENSOR_SHUTDOWN();    \
378 
+}
379 
+
380 
+
381 
+
382 
+//
383 
+// This pin controls if the battery voltage can be read
384 
+//
385 
+#define BATTERY_READ_CONTROL_PDIR ( P4DIR )
386 
+#define BATTERY_READ_CONTROL_POUT ( P4OUT )
387 
+#define BATTERY_READ_CONTROL_PIN  ( BIT6 )
388 
+
389 
+#define BATTERY_SENSE_INPUT_PDIR ( P7DIR )
390 
+#define BATTERY_SENSE_INPUT_PSEL ( P7SEL )
391 
+#define BATTERY_SENSE_INPUT_PIN  ( BIT7 )
392 
+
393 
+#define BATTERY_SENSE_INIT()                             \
394 
+{                                                        \
395 
+  BATTERY_READ_CONTROL_PDIR |= BATTERY_READ_CONTROL_PIN; \
396 
+  BATTERY_SENSE_INPUT_PDIR &= ~BATTERY_SENSE_INPUT_PIN;  \
397 
+  BATTERY_SENSE_INPUT_PSEL |= BATTERY_SENSE_INPUT_PIN;   \
398 
+  BATTERY_SENSE_DISABLE();                               \
399 
+}
400 
+
401 
+#define BATTERY_SENSE_ENABLE() \
402 
+{                                                        \
403 
+  BATTERY_READ_CONTROL_POUT |= BATTERY_READ_CONTROL_PIN; \
404 
+}
405 
+
406 
+#define BATTERY_SENSE_DISABLE() \
407 
+{                                                         \
408 
+  BATTERY_READ_CONTROL_POUT &= ~BATTERY_READ_CONTROL_PIN; \
409 
+}
410 
+
411 
+//
412 
+// hardware configuration is a voltage divider to ADC input
413 
+//
414 
+#define HARDWARE_CFG_CONTROL_PDIR ( P5DIR )
415 
+#define HARDWARE_CFG_CONTROL_POUT ( P5OUT )
416 
+#define HARDWARE_CFG_CONTROL_PIN  ( BIT0 )
417 
+
418 
+#define HARDWARE_CFG_INPUT_PDIR ( P7DIR )
419 
+#define HARDWARE_CFG_INPUT_PSEL ( P7SEL )
420 
+#define HARDWARE_CFG_INPUT_PIN  ( BIT5 )
421 
+
422 
+#define HARDWARE_CFG_SENSE_INIT()                        \
423 
+{                                                        \
424 
+  HARDWARE_CFG_CONTROL_PDIR |= HARDWARE_CFG_CONTROL_PIN; \
425 
+  HARDWARE_CFG_INPUT_PDIR &= ~HARDWARE_CFG_INPUT_PIN;    \
426 
+  HARDWARE_CFG_INPUT_PSEL |= HARDWARE_CFG_INPUT_PIN;     \
427 
+  HARDWARE_CFG_SENSE_DISABLE();                          \
428 
+}
429 
+
430 
+#define HARDWARE_CFG_SENSE_ENABLE()                         \
431 
+{                                                           \
432 
+  HARDWARE_CFG_CONTROL_POUT |= HARDWARE_CFG_CONTROL_PIN;    \
433 
+}
434 
+
435 
+#define HARDWARE_CFG_SENSE_DISABLE()                        \
436 
+{                                                           \
437 
+  HARDWARE_CFG_CONTROL_POUT &= ~HARDWARE_CFG_CONTROL_PIN;   \
438 
+}
439 
+
440 
+
441 
+#define APPLE_SDA_PDIR ( P10DIR )
442 
+#define APPLE_SDA_POUT ( P10OUT )
443 
+#define APPLE_SDA_PIN  ( BIT1 )
444 
+
445 
+#define APPLE_SCL_PDIR ( P10DIR )
446 
+#define APPLE_SCL_POUT ( P10OUT )
447 
+#define APPLE_SCL_PIN  ( BIT2 )
448 
+
449 
+#define APPLE_POWER_PDIR ( P4DIR )
450 
+#define APPLE_POWER_POUT ( P4OUT )
451 
+#define APPLE_POWER_PIN  ( BIT5 )
452 
+
453 
+/* power enable is active low */
454 
+#define APPLE_POWER_ENABLE()   { APPLE_POWER_POUT &= ~APPLE_POWER_PIN; }
455 
+#define APPLE_POWER_DISABLE()  { APPLE_POWER_POUT |= APPLE_POWER_PIN; }
456 
+
457 
+#define APPLE_POWER_CONFIG()   { \
458 
+  APPLE_POWER_PDIR |= APPLE_POWER_PIN; \
459 
+  APPLE_POWER_DISABLE(); \
460 
+}
461 
+
462 
+
463 
+/* since the apple chip is currently not powered
464 
+ * the pins should be at 0 instead of 1
465 
+ */
466 
+#define APPLE_I2C_PIN_CONFIG() {    \
467 
+  APPLE_SDA_PDIR |= APPLE_SDA_PIN;  \
468 
+  APPLE_SDA_POUT &= ~APPLE_SDA_PIN; \
469 
+  APPLE_SCL_PDIR |= APPLE_SCL_PIN;  \
470 
+  APPLE_SCL_POUT &= ~APPLE_SCL_PIN; \
471 
+}
472 
+
473 
+#define APPLE_CONFIG() {  \
474 
+  APPLE_POWER_CONFIG();   \
475 
+  APPLE_I2C_PIN_CONFIG(); \
476 
+}
477 
+
478 
+#define SRAM_SCLK_PSEL ( P3SEL )
479 
+#define SRAM_SCLK_PDIR ( P3DIR )
480 
+#define SRAM_SCLK_POUT ( P3OUT )
481 
+#define SRAM_SCLK_PIN  ( BIT0 )
482 
+
483 
+#define SRAM_SOMI_PSEL ( P3SEL )
484 
+#define SRAM_SOMI_PDIR ( P3DIR )
485 
+#define SRAM_SOMI_POUT ( P3OUT )
486 
+#define SRAM_SOMI_PIN  ( BIT5 )
487 
+
488 
+#define SRAM_SIMO_PSEL ( P3SEL )
489 
+#define SRAM_SIMO_PDIR ( P3DIR )
490 
+#define SRAM_SIMO_POUT ( P3OUT )
491 
+#define SRAM_SIMO_PIN  ( BIT4 )
492 
+
493 
+#define SRAM_CSN_PDIR ( P9DIR )
494 
+#define SRAM_CSN_POUT ( P9OUT )
495 
+#define SRAM_CSN_PIN  ( BIT6)
496 
+
497 
+#define SRAM_HOLDN_PDIR ( P9DIR )
498 
+#define SRAM_HOLDN_POUT ( P9OUT )
499 
+#define SRAM_HOLDN_PIN  ( BIT7 )
500 
+
501 
+#define CONFIG_SRAM_PINS() \
502 
+{                                     \
503 
+  SRAM_CSN_PDIR |= SRAM_CSN_PIN;      \
504 
+  SRAM_CSN_POUT |= SRAM_CSN_PIN;      \
505 
+  SRAM_HOLDN_PDIR |= SRAM_HOLDN_PIN;  \
506 
+  SRAM_HOLDN_POUT |= SRAM_HOLDN_PIN;  \
507 
+}
508 
+
509 
+#define SRAM_CSN_ASSERT() { SRAM_CSN_POUT &= ~SRAM_CSN_PIN; }
510 
+
511 
+#define SRAM_CSN_DEASSERT() { \
512 
+  WAIT_FOR_SRAM_SPI_SHIFT_COMPLETE(); \
513 
+  SRAM_CSN_POUT |= SRAM_CSN_PIN; \
514 
+}
515 
+
516 
+/* wait for shift to complete ( ~3 us ) */
517 
+#define WAIT_FOR_SRAM_SPI_SHIFT_COMPLETE() { while( (UCA0STAT & 0x01) != 0 ); }
518 
+
519 
+#define ACCELEROMETER_SDA_PIN  ( BIT7 )
520 
+#define ACCELEROMETER_SDA_PSEL ( P3SEL )
521 
+#define ACCELEROMETER_SDA_POUT ( P3OUT )
522 
+#define ACCELEROMETER_SDA_PDIR ( P3OUT )
523 
+#define ACCELEROMETER_SDA_PREN ( P1REN )
524 
+
525 
+#define ACCELEROMETER_SCL_PIN  ( BIT4 )
526 
+#define ACCELEROMETER_SCL_PSEL ( P5SEL )
527 
+#define ACCELEROMETER_SCL_POUT ( P5OUT )
528 
+#define ACCELEROMETER_SCL_PDIR ( P5OUT )
529 
+#define ACCELEROMETER_SCL_PREN ( P5REN )
530 
+
531 
+#define ACCELEROMETER_INT_PIN  ( BIT7 )
532 
+#define ACCELEROMETER_INT_PDIR ( P1DIR )
533 
+#define ACCELEROMETER_INT_PSEL ( P1SEL )
534 
+#define ACCELEROMETER_INT_PIFG ( P1IFG )
535 
+#define ACCELEROMETER_INT_PIE  ( P1IE )
536 
+
537 
+#define ACCELEROMETER_POWER_POUT ( P9OUT )
538 
+#define ACCELEROMETER_POWER_PDIR ( P9DIR )
539 
+#define ACCELEROMETER_POWER_PINS ( BIT1 | BIT2 )
540 
+
541 
+/* this is for reference only (it doesn't control anything) */
542 
+#define ACCELEROMETER_INT_NUM (PIN7_INT)
543 
+
544 
+#define LED4_PIN ( BIT2 )
545 
+#define LED5_PIN ( BIT3 )
546 
+#define LED6_PIN ( BIT4 )
547 
+#define LED7_PIN ( BIT5 )
548 
+
549 
+#define LEDS_PDIR ( P8DIR )
550 
+#define LEDS_POUT ( P8OUT )
551 
+
552 
+#define LED4_ON() { LEDS_POUT |= LED4_PIN; }
553 
+#define LED5_ON() { LEDS_POUT |= LED5_PIN; }
554 
+#define LED6_ON() { LEDS_POUT |= LED6_PIN; }
555 
+#define LED7_ON() { LEDS_POUT |= LED7_PIN; }
556 
+
557 
+#define LED4_OFF() { LEDS_POUT &= ~LED4_PIN; }
558 
+#define LED5_OFF() { LEDS_POUT &= ~LED5_PIN; }
559 
+#define LED6_OFF() { LEDS_POUT &= ~LED6_PIN; }
560 
+#define LED7_OFF() { LEDS_POUT &= ~LED7_PIN; }
561 
+
562 
+#define LED4_TOGGLE() { LEDS_POUT ^= LED4_PIN; }
563 
+#define LED5_TOGGLE() { LEDS_POUT ^= LED5_PIN; }
564 
+#define LED6_TOGGLE() { LEDS_POUT ^= LED6_PIN; }
565 
+#define LED7_TOGGLE() { LEDS_POUT ^= LED7_PIN; }
566 
+
567 
+#define CONFIG_LED_PINS() { \
568 
+  LEDS_PDIR |= LED4_PIN | LED5_PIN | LED6_PIN | LED7_PIN; \
569 
+  LED4_OFF(); LED5_OFF(); LED6_OFF(); LED7_OFF(); \
570 
+}
571 
+
572 
+#define DEBUG1_PIN ( BIT1 )
573 
+#define DEBUG3_PIN ( BIT4 )
574 
+#define DEBUG4_PIN ( BIT7 )
575 
+#define DEBUG5_PIN ( BIT6 )
576 
+
577 
+#define DEBUG1_PDIR ( P5DIR )
578 
+#define DEBUG3_PDIR ( P7DIR )
579 
+#define DEBUG4_PDIR ( P6DIR )
580 
+#define DEBUG5_PDIR ( P7DIR )
581 
+
582 
+#define DEBUG1_POUT ( P5OUT )
583 
+#define DEBUG3_POUT ( P7OUT )
584 
+#define DEBUG4_POUT ( P6OUT )
585 
+#define DEBUG5_POUT ( P7OUT )
586 
+
587 
+#define DEBUG1_HIGH() { DEBUG1_POUT |= DEBUG1_PIN; }
588 
+#define DEBUG3_HIGH() { DEBUG3_POUT |= DEBUG3_PIN; }
589 
+#define DEBUG4_HIGH() { DEBUG4_POUT |= DEBUG4_PIN; }
590 
+#define DEBUG5_HIGH() { DEBUG5_POUT |= DEBUG5_PIN; }
591 
+
592 
+#define DEBUG1_LOW() { DEBUG1_POUT &= ~DEBUG1_PIN; }
593 
+#define DEBUG3_LOW() { DEBUG3_POUT &= ~DEBUG3_PIN; }
594 
+#define DEBUG4_LOW() { DEBUG4_POUT &= ~DEBUG4_PIN; }
595 
+#define DEBUG5_LOW() { DEBUG5_POUT &= ~DEBUG5_PIN; }
596 
+
597 
+#define DEBUG1_PULSE() { DEBUG1_HIGH(); DEBUG1_LOW(); }
598 
+#define DEBUG3_PULSE() { DEBUG3_HIGH(); DEBUG3_LOW(); }
599 
+#define DEBUG4_PULSE() { DEBUG4_HIGH(); DEBUG4_LOW(); }
600 
+#define DEBUG5_PULSE() { DEBUG5_HIGH(); DEBUG5_LOW(); }
601 
+
602 
+#define DEBUG1_TOGGLE() { DEBUG1_POUT ^= DEBUG1_PIN; }
603 
+#define DEBUG3_TOGGLE() { DEBUG3_POUT ^= DEBUG3_PIN; }
604 
+#define DEBUG4_TOGGLE() { DEBUG4_POUT ^= DEBUG4_PIN; }
605 
+#define DEBUG5_TOGGLE() { DEBUG5_POUT ^= DEBUG5_PIN; }
606 
+
607 
+#define CONFIG_DEBUG_PINS() { \
608 
+  DEBUG1_PDIR |= DEBUG1_PIN;  \
609 
+  DEBUG3_PDIR |= DEBUG3_PIN;  \
610 
+  DEBUG4_PDIR |= DEBUG4_PIN;  \
611 
+  DEBUG5_PDIR |= DEBUG5_PIN;  \
612 
+  DEBUG1_POUT &= ~DEBUG1_PIN; \
613 
+  DEBUG3_POUT &= ~DEBUG3_PIN; \
614 
+  DEBUG4_POUT &= ~DEBUG4_PIN; \
615 
+  DEBUG5_POUT &= ~DEBUG5_PIN; \
616 
+}
617 
+
618 
+
619 
+
620 
+/*
621 
+ * Sideband signals (for lack of another word)
622 
+ */
623 
+#define BT_CLK_REQ_PDIR     ( P1DIR )
624 
+#define BT_CLK_REQ_POUT     ( P1OUT )
625 
+#define BT_CLK_REQ_PIN      ( BIT4 )
626 
+
627 
+#define BT_IO1_PDIR     ( P1DIR )
628 
+#define BT_IO1_POUT     ( P1OUT )
629 
+#define BT_IO1_PIN      ( BIT5 )
630 
+
631 
+#define BT_IO2_PDIR     ( P1DIR )
632 
+#define BT_IO2_POUT     ( P1OUT )
633 
+#define BT_IO2_PIN      ( BIT6 )
634 
+
635 
+/******************************************************************************/
636 
+
637 
+/* peripheral mapping for accelerometer */
638 
+#define ACCELEROMETER_CTL0  ( UCB1CTL0 )
639 
+#define ACCELEROMETER_CTL1  ( UCB1CTL1 )
640 
+#define ACCELEROMETER_BR0   ( UCB1BR0 )
641 
+#define ACCELEROMETER_BR1   ( UCB1BR1 )
642 
+#define ACCELEROMETER_I2CSA ( UCB1I2CSA )
643 
+#define ACCELEROMETER_IE    ( UCB1IE )
644 
+#define ACCELEROMETER_IFG   ( UCB1IFG )
645 
+#define ACCELEROMETER_TXBUF ( UCB1TXBUF )
646 
+#define ACCELEROMETER_RXBUF ( UCB1RXBUF )
647 
+#define ACCELEROMETER_STAT  ( UCB1STAT )
648 
+/* interrupt mapping for accelerometer */
649 
+#define USCI_ACCELEROMETER_VECTOR ( USCI_B1_VECTOR )
650 
+#define USCI_ACCELEROMETER_IV     ( UCB1IV )
651 
+
652 
+
653 
+
654 
+
655 
+#endif // HAL_DEVBOARD_V2_DEFS_H
656 
+
657 
+
658 
+
659 
+
660 
+