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Power saving changes, add new fonts, bitmaps and screens

Nils Faerber authored on 19/05/2013 00:07:04
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metawatch/F5xx_F6xx_Core_Lib/HAL_UCS.c
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+/*******************************************************************************
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+ *
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+ * HAL_UCS.c
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+ * Provides Functions to Initialize the UCS/FLL and clock sources
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+ *
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+ *
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+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
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+ *
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+ *
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+ *  Redistribution and use in source and binary forms, with or without
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+ *  modification, are permitted provided that the following conditions
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+ *  are met:
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+ *
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+ *    Redistributions of source code must retain the above copyright
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+ *    notice, this list of conditions and the following disclaimer.
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+ *
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+ *    Redistributions in binary form must reproduce the above copyright
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+ *    notice, this list of conditions and the following disclaimer in the
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+ *    documentation and/or other materials provided with the
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+ *    distribution.
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+ *
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+ *    Neither the name of Texas Instruments Incorporated nor the names of
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+ *    its contributors may be used to endorse or promote products derived
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+ *    from this software without specific prior written permission.
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+ *
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+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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+ *
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+ * Created: Version 1.0 11/24/2009
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+ * Updated: Version 2.0 12/15/2010
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+ *          Added Functions: XT2_Stop() and XT1_Stop()
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+ *          Modified all functions to preserve drive settings
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+ *
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+ ******************************************************************************/
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+
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+#include "msp430.h"
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+#include "HAL_UCS.h"
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+// #include "hal_calibration.h"
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+
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+/*******************************************************************************
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+ * Check and define required Defines
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+ ******************************************************************************/
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+#ifndef XT1LFOFFG               // Defines if not available in header file
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+#define XT1LFOFFG   0
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+#endif
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+
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+#ifndef XT1HFOFFG               // Defines if not available in header file
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+#define XT1HFOFFG   0
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+#endif
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+
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+#ifndef XT2OFFG                 // Defines if not available in header file
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+#define XT2OFFG     0
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+#endif
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+
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+#ifndef XTS                     // Defines if not available in header file
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+#define XTS         0
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+#endif
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+
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+#ifndef XT2DRIVE_3              // Defines if not available in header file
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+#define XT2DRIVE_3  0
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+#endif
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+
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+
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+/*******************************************************************************
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+ * \brief   Initializes FLL of the UCS
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+ *
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+ * \param fsystem  Required system frequency (MCLK) in kHz
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+ * \param ratio    Ratio between fsystem and FLLREFCLK
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+ ******************************************************************************/
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+static void Init_FLL(unsigned int fsystem, unsigned int ratio);
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+
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+
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+#if 0
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+void LFXT_Start(unsigned int xtdrive)
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+{
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+  // If the drive setting is not already set to maximum
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+  // Set it to max for LFXT startup
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+  if ((UCSCTL6 & XT1DRIVE_3)!= XT1DRIVE_3) {
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+    UCSCTL6_L |= XT1DRIVE1_L + XT1DRIVE0_L; // Highest drive setting for XT1startup
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+  }
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+
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+  while (SFRIFG1 & OFIFG) {   // Check OFIFG fault flag
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+    UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT1HFOFFG+XT2OFFG); // Clear OSC flaut Flags fault flags
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+    SFRIFG1 &= ~OFIFG;        // Clear OFIFG fault flag
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+  }
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+
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+  UCSCTL6 = (UCSCTL6 & ~(XT1DRIVE_3)) | (xtdrive); // set requested Drive mode
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+}
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+#endif
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+
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+unsigned int LFXT_Start_Timeout(unsigned int xtdrive, unsigned int timeout)
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+{
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+  // add in capacitor setting
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+  //SetOscillatorCapacitorValues();
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+
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+  // If the drive setting is not already set to maximum
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+  // Set it to max for LFXT startup
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+  if ((UCSCTL6 & XT1DRIVE_3)!= XT1DRIVE_3) {
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+   UCSCTL6_L |= XT1DRIVE1_L+XT1DRIVE0_L; // Highest drive setting for XT1startup
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+  }
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+
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+  while ((SFRIFG1 & OFIFG) && timeout--){   // Check OFIFG fault flag
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+    UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT1HFOFFG+XT2OFFG); // Clear OSC flaut Flags fault flags
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+    SFRIFG1 &= ~OFIFG;        // Clear OFIFG fault flag
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+  }
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+
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+  UCSCTL6 = (UCSCTL6 & ~(XT1DRIVE_3)) |(xtdrive); // set Drive mode
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+
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+  // add in capacitor setting
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+  //SetOscillatorCapacitorValues();
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+
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+  if (timeout)
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+    return (UCS_STATUS_OK);
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+  else
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+    return (UCS_STATUS_ERROR);
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+}
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+
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+#if 0
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+void XT1_Start(unsigned int xtdrive)
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+{
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+  // Check if drive value is the expected one
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+  if ((UCSCTL6 & XT1DRIVE_3) != xtdrive) {
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+    UCSCTL6 &= ~XT1DRIVE_3;                 // Clear XT1drive field
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+    UCSCTL6 |= xtdrive;                     // Set requested value
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+  }
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+
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+  UCSCTL6 &= ~XT1OFF;                       // Enable XT1
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+  UCSCTL6 |= XTS;                           // Enable HF mode
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+
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+  while (SFRIFG1 & OFIFG) {   // Check OFIFG fault flag
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+    UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT1HFOFFG+XT2OFFG); // Clear OSC flaut Flags
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+    SFRIFG1 &= ~OFIFG;        // Clear OFIFG fault flag
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+  }
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+}
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+
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+unsigned int XT1_Start_Timeout(unsigned int xtdrive, unsigned int timeout)
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+{
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+  // Check if drive value is the expected one
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+  if ((UCSCTL6 & XT1DRIVE_3) != xtdrive) {
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+    UCSCTL6 &= ~XT1DRIVE_3;                 // Clear XT1drive field
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+    UCSCTL6 |= xtdrive;                     // Set requested value
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+  }
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+
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+  UCSCTL6 &= ~XT1OFF;                       // Enable XT1
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+  UCSCTL6 |= XTS;                           // Enable HF mode
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+
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+  while ((SFRIFG1 & OFIFG) && timeout--) {  // Check OFIFG fault flag
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+    UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT1HFOFFG+XT2OFFG); // Clear OSC flaut Flags
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+    SFRIFG1 &= ~OFIFG;                      // Clear OFIFG fault flag
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+  }
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+
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+  if (timeout) {
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+    return UCS_STATUS_OK;
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+  }
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+  else {
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+    return UCS_STATUS_ERROR;
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+  }
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+}
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+
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+void XT1_Bypass(void)
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+{
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+  UCSCTL6 |= XT1BYPASS;
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+
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+  while (SFRIFG1 & OFIFG) {   // Check OFIFG fault flag
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+    UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT1HFOFFG+XT2OFFG); // Clear OSC flaut Flags
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+    SFRIFG1 &= ~OFIFG;        // Clear OFIFG fault flag
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+  }
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+}
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+#endif
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+
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+void XT1_Stop(void)
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+{
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+  UCSCTL6 |= XT1OFF;                         // Switch off XT1 oscillator
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+}
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+
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+#if 0
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+void XT2_Start(unsigned int xtdrive)
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+{
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+  // Check if drive value is the expected one
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+  if ((UCSCTL6 & XT2DRIVE_3) != xtdrive) {
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+    UCSCTL6 &= ~XT2DRIVE_3;                 // Clear XT2drive field
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+    UCSCTL6 |= xtdrive;                     // Set requested value
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+  }
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+
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+  UCSCTL6 &= ~XT2OFF;
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+
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+  while (SFRIFG1 & OFIFG) {                 // Check OFIFG fault flag
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+    UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT1HFOFFG+XT2OFFG); // Clear OSC flaut Flags
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+    SFRIFG1 &= ~OFIFG;                      // Clear OFIFG fault flag
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+  }
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+}
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+
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+unsigned int XT2_Start_Timeout(unsigned int xtdrive, unsigned int timeout)
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+{
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+  // Check if drive value is the expected one
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+  if ((UCSCTL6 & XT2DRIVE_3) != xtdrive)  {
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+    UCSCTL6 &= ~XT2DRIVE_3;                 // Clear XT2drive field
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+    UCSCTL6 |= xtdrive;                     // Set requested value
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+  }
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+
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+  UCSCTL6 &= ~XT2OFF;
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+
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+  while ((SFRIFG1 & OFIFG) && timeout--) {  // Check OFIFG fault flag
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+    UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT1HFOFFG+XT2OFFG); // Clear OSC flaut Flags
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+    SFRIFG1 &= ~OFIFG;        // Clear OFIFG fault flag
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+  }
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+
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+  if (timeout) {
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+    return UCS_STATUS_OK;
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+  }
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+  else {
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+    return UCS_STATUS_ERROR;
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+  }
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+}
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+
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+void XT2_Bypass(void)
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+{
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+#ifdef XT2BYPASS              // On devices without XT2 this function will be empty
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+  UCSCTL6 |= XT2BYPASS;
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+
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+  while (SFRIFG1 & OFIFG) {   // Check OFIFG fault flag
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+    UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT1HFOFFG+XT2OFFG); // Clear OSC flaut Flags
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+    SFRIFG1 &= ~OFIFG;        // Clear OFIFG fault flag
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+  }
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+#endif
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+}
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+
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+void XT2_Stop(void)
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+{
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+  UCSCTL6 |= XT2OFF;                         // Switch off XT2 oscillator
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+}
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+#endif
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+
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+void Init_FLL_Settle(unsigned int fsystem, unsigned int ratio)
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+{
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+  volatile unsigned int x;
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+
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+  // x = ratio * 32;
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+  x = ratio << 5;
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+  Init_FLL(fsystem, ratio);
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+
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+  /* from changes in Init_FLL we know that fll is now enabled */
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+  while (x--) {
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+   __delay_cycles(30);
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+  }
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+}
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+
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+static void Init_FLL(unsigned int fsystem, unsigned int ratio)
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+{
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+  unsigned int d, dco_div_bits;
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+  unsigned int mode;
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+
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+#if 0
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+  unsigned int srRegisterState;
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+#endif
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+
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+  mode = 0;
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+
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+  /* we only run this at startup and we want the fll enabled on exit */
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+#if 0
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+  // Save actual state of FLL loop control, then disable it. This is needed to
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+  // prevent the FLL from acting as we are making fundamental modifications to
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+  // the clock setup.
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+  srRegisterState = __get_SR_register() & SCG0;
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+#endif
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+
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+  d = ratio;
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+  dco_div_bits = FLLD__2;        // Have at least a divider of 2
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+
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+  if (fsystem > 16000) {
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+    d >>= 1 ;
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+    mode = 1;
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+  }
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+  else {
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+    fsystem <<= 1;               // fsystem = fsystem * 2
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+  }
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+
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+  while (d > 512) {
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+    dco_div_bits = dco_div_bits + FLLD0;  // Set next higher div level
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+    d >>= 1;
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+  }
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+
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+  // Disable FLL
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+  __bis_SR_register(SCG0);
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+
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+  UCSCTL0 = 0x0000;              // Set DCO to lowest Tap
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+
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+  UCSCTL2 &= ~(0x03FF);          // Reset FN bits
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+  UCSCTL2 = dco_div_bits | (d - 1);
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+
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+  if (fsystem <= 630)            //           fsystem < 0.63MHz
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+	UCSCTL1 = DCORSEL_0;
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+  else if (fsystem <  1250)      // 0.63MHz < fsystem < 1.25MHz
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+	UCSCTL1 = DCORSEL_1;
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+  else if (fsystem <  2500)      // 1.25MHz < fsystem <  2.5MHz
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+	UCSCTL1 = DCORSEL_2;
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+  else if (fsystem <  5000)      // 2.5MHz  < fsystem <    5MHz
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+	UCSCTL1 = DCORSEL_3;
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+  else if (fsystem <  10000)     // 5MHz    < fsystem <   10MHz
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+	UCSCTL1 = DCORSEL_4;
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+  else if (fsystem <  20000)     // 10MHz   < fsystem <   20MHz
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+	UCSCTL1 = DCORSEL_5;
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+  else if (fsystem <  40000)     // 20MHz   < fsystem <   40MHz
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+	UCSCTL1 = DCORSEL_6;
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+  else
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+	UCSCTL1 = DCORSEL_7;
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+
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+  // Re-enable FLL
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+  __bic_SR_register(SCG0);
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+
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+  while (SFRIFG1 & OFIFG) {                               // Check OFIFG fault flag
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+    UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT1HFOFFG+XT2OFFG);     // Clear OSC flaut Flags
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+    SFRIFG1 &= ~OFIFG;                                    // Clear OFIFG fault flag
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+  }
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+
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+  /* Init fll is only run at startup - We want the fll enabled when
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+   * this function is complete (so don't save a restore setting)
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+   */
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+#if 0
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+  // Restore previous SCG0
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+  __bis_SR_register(srRegisterState);
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+#endif
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+
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+  if (mode == 1) {                              		  // fsystem > 16000
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+    SELECT_MCLK_SMCLK(SELM__DCOCLK + SELS__DCOCLK);       // Select DCOCLK
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+  }
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+  else {
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+    SELECT_MCLK_SMCLK(SELM__DCOCLKDIV + SELS__DCOCLKDIV); // Select DCODIVCLK
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+  }
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+
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+}