... | ... |
@@ -99,11 +99,22 @@ |
99 | 99 |
#define TFUM (1 << 0) |
100 | 100 |
|
101 | 101 |
/* INT_SRC_REG2 */ |
102 |
-#define INT_TAP_SINGLE (0x04) |
|
103 |
-#define INT_TAP_DOUBLE (0x08) |
|
102 |
+#define INT_TPS 0x01 |
|
103 |
+#define INT_WUFS 0x02 |
|
104 |
+#define INT_TAP_SINGLE 0x04 |
|
105 |
+#define INT_TAP_DOUBLE 0x08 |
|
106 |
+#define INT_DRDY 0x10 |
|
104 | 107 |
|
105 |
-/* for readability */ |
|
106 |
-#define ONE_BYTE ( 1 ) |
|
107 | 108 |
|
108 |
-#endif |
|
109 |
+void mw_acc_init_i2c(void); |
|
110 |
+void mw_acc_disable_i2c(void); |
|
111 |
+void mw_acc_i2c_read(const uint8_t RegisterAddress, uint8_t *pData, const uint8_t Length); |
|
112 |
+void mw_acc_i2c_write(uint8_t RegisterAddress, uint8_t *pData, uint8_t Length); |
|
113 |
+ |
|
114 |
+void mw_acc_init(void); |
|
115 |
+void mw_acc_enable(void); |
|
116 |
+void mw_acc_disable(void); |
|
117 |
+void mw_acc_read(int16_t *x, int16_t *y, int16_t *z); |
|
118 |
+void mw_acc_handle_irq(void); |
|
109 | 119 |
|
120 |
+#endif |
1 | 1 |
new file mode 100644 |
... | ... |
@@ -0,0 +1,109 @@ |
1 |
+#ifndef _MW_ACC_H |
|
2 |
+#define _MW_ACC_H |
|
3 |
+ |
|
4 |
+#define KIONIX_DEVICE_ADDRESS ( 0x0F ) |
|
5 |
+ |
|
6 |
+/* KIONIX accelerometer register addresses */ |
|
7 |
+#define KIONIX_XOUT_HPF_L ( 0x00 ) |
|
8 |
+#define KIONIX_XOUT_HPF_H ( 0x01 ) |
|
9 |
+#define KIONIX_YOUT_HPF_L ( 0x02 ) |
|
10 |
+#define KIONIX_YOUT_HPF_H ( 0x03 ) |
|
11 |
+#define KIONIX_ZOUT_HPF_L ( 0x04 ) |
|
12 |
+#define KIONIX_ZOUT_HPF_H ( 0x05 ) |
|
13 |
+#define KIONIX_XOUT_L ( 0x06 ) |
|
14 |
+#define KIONIX_XOUT_H ( 0x07 ) |
|
15 |
+#define KIONIX_YOUT_L ( 0x08 ) |
|
16 |
+#define KIONIX_YOUT_H ( 0x09 ) |
|
17 |
+#define KIONIX_ZOUT_L ( 0x0A ) |
|
18 |
+#define KIONIX_ZOUT_H ( 0x0B ) |
|
19 |
+#define KIONIX_DCST_RESP ( 0x0C ) |
|
20 |
+#define KIONIX_WHO_AM_I ( 0x0F ) |
|
21 |
+#define KIONIX_TILT_POS_CUR ( 0x10 ) |
|
22 |
+#define KIONIX_TILT_POS_PRE ( 0x11 ) |
|
23 |
+#define KIONIX_INT_SRC_REG1 ( 0x15 ) |
|
24 |
+#define KIONIX_INT_SRC_REG2 ( 0x16 ) |
|
25 |
+#define KIONIX_STATUS_REG ( 0x18 ) |
|
26 |
+#define KIONIX_INT_REL ( 0x1A ) |
|
27 |
+#define KIONIX_CTRL_REG1 ( 0x1B ) |
|
28 |
+#define KIONIX_CTRL_REG2 ( 0x1C ) |
|
29 |
+#define KIONIX_CTRL_REG3 ( 0x1D ) |
|
30 |
+#define KIONIX_INT_CTRL_REG1 ( 0x1E ) |
|
31 |
+#define KIONIX_INT_CTRL_REG2 ( 0x1F ) |
|
32 |
+#define KIONIX_INT_CTRL_REG3 ( 0x20 ) |
|
33 |
+#define KIONIX_DATA_CTRL_REG ( 0x21 ) |
|
34 |
+#define KIONIX_TILT_TIMER ( 0x28 ) |
|
35 |
+#define KIONIX_WUF_TIMER ( 0x29 ) |
|
36 |
+#define KIONIX_TDT_TIMER ( 0x2B ) |
|
37 |
+#define KIONIX_TDT_H_THRESH ( 0x2C ) |
|
38 |
+#define KIONIX_TDT_L_THRESH ( 0x2D ) |
|
39 |
+#define KIONIX_TDT_TAP_TIMER ( 0x2E ) |
|
40 |
+#define KIONIX_TDT_TOTAL_TIMER ( 0x2F ) |
|
41 |
+#define KIONIX_TDT_LATENCY_TIMER ( 0x30 ) |
|
42 |
+#define KIONIX_TDT_WINDOW_TIMER ( 0x31 ) |
|
43 |
+#define KIONIX_SELF_TEST ( 0x3A ) |
|
44 |
+#define KIONIX_WUF_THRESH ( 0x5A ) |
|
45 |
+#define KIONIX_TILT_ANGLE ( 0x5C ) |
|
46 |
+#define KIONIX_HYST_SET ( 0x5F ) |
|
47 |
+ |
|
48 |
+/* CTRL_REG1 */ |
|
49 |
+#define PC1_STANDBY_MODE ( 0 << 7 ) |
|
50 |
+#define PC1_OPERATING_MODE ( 1 << 7 ) |
|
51 |
+#define RESOLUTION_8BIT ( 0 << 6 ) |
|
52 |
+#define RESOLUTION_12BIT ( 1 << 6 ) |
|
53 |
+#define DRDYE_DATA_AVAILABLE ( 1 << 5 ) |
|
54 |
+#define WUF_ENABLE ( 1 << 1 ) |
|
55 |
+#define TAP_ENABLE_TDTE ( 1 << 2 ) |
|
56 |
+#define TILT_ENABLE_TPE ( 1 << 0 ) |
|
57 |
+ |
|
58 |
+/* CTRL_REG2 */ |
|
59 |
+#define TILT_LEM (1 << 5 ) |
|
60 |
+#define TILT_RIM (1 << 4 ) |
|
61 |
+#define TILT_DOM (1 << 3 ) |
|
62 |
+#define TILT_UPM (1 << 2 ) |
|
63 |
+#define TILT_FDM (1 << 1 ) |
|
64 |
+#define TILT_FUM (1 << 0 ) |
|
65 |
+ |
|
66 |
+/* CTRL_REG3 */ |
|
67 |
+#define SRST ( 1 << 7 ) |
|
68 |
+#define TILT_ODR_1_6HZ ( 0 << 5 ) |
|
69 |
+#define TILT_ODR_6_3HZ ( 1 << 5 ) |
|
70 |
+#define TILT_ODR_12_5HZ ( 2 << 5 ) |
|
71 |
+#define TILT_ODR_50HZ ( 3 << 5 ) |
|
72 |
+#define DCST ( 1 << 4 ) |
|
73 |
+#define TAP_ODR_50HZ ( 0 << 2 ) |
|
74 |
+#define TAP_ODR_100HZ ( 1 << 2 ) |
|
75 |
+#define TAP_ODR_200HZ ( 2 << 2 ) |
|
76 |
+#define TAP_ODR_400HZ ( 3 << 2 ) |
|
77 |
+#define WUF_ODR_25HZ ( 0 << 0 ) |
|
78 |
+#define WUF_ODR_50HZ ( 1 << 0 ) |
|
79 |
+#define WUF_ODR_100HZ ( 2 << 0 ) |
|
80 |
+#define WUF_ODR_200HZ ( 3 << 0 ) |
|
81 |
+ |
|
82 |
+/* INT_CTRL_REG1 */ |
|
83 |
+#define IEN ( 1 << 5 ) |
|
84 |
+#define IEA ( 1 << 4 ) |
|
85 |
+#define IEL ( 1 << 3 ) |
|
86 |
+#define IEU ( 1 << 2 ) |
|
87 |
+ |
|
88 |
+/* INT_CTRL_REG2 */ |
|
89 |
+#define XBW ( 1 << 7 ) |
|
90 |
+#define YBW ( 1 << 6 ) |
|
91 |
+#define ZBW ( 1 << 5 ) |
|
92 |
+ |
|
93 |
+/* INT_CTRL_REG3 */ |
|
94 |
+#define TLEM (1 << 5) |
|
95 |
+#define TRIM (1 << 4) |
|
96 |
+#define TDOM (1 << 3) |
|
97 |
+#define TUPM (1 << 2) |
|
98 |
+#define TFDM (1 << 1) |
|
99 |
+#define TFUM (1 << 0) |
|
100 |
+ |
|
101 |
+/* INT_SRC_REG2 */ |
|
102 |
+#define INT_TAP_SINGLE (0x04) |
|
103 |
+#define INT_TAP_DOUBLE (0x08) |
|
104 |
+ |
|
105 |
+/* for readability */ |
|
106 |
+#define ONE_BYTE ( 1 ) |
|
107 |
+ |
|
108 |
+#endif |
|
109 |
+ |