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Power saving changes, add new fonts, bitmaps and screens

Nils Faerber authored on 19/05/2013 00:07:04
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metawatch/F5xx_F6xx_Core_Lib/HAL_PMM.c
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+/*******************************************************************************
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+ *
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+ * HAL_PMM.c
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+ * Power Management Module Library for MSP430F5xx/6xx family
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+ *
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+ *
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+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
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+ *
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+ *
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+ *  Redistribution and use in source and binary forms, with or without
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+ *  modification, are permitted provided that the following conditions
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+ *  are met:
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+ *
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+ *    Redistributions of source code must retain the above copyright
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+ *    notice, this list of conditions and the following disclaimer.
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+ *
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+ *    Redistributions in binary form must reproduce the above copyright
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+ *    notice, this list of conditions and the following disclaimer in the
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+ *    documentation and/or other materials provided with the
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+ *    distribution.
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+ *
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+ *    Neither the name of Texas Instruments Incorporated nor the names of
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+ *    its contributors may be used to endorse or promote products derived
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+ *    from this software without specific prior written permission.
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+ *
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+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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+ *
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+ * Created: Version 1.0 11/24/2009
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+ * Updated: Version 2.0 12/15/2010
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+ *          Modified SetVcoreUp() and SetVcoreDown() functions
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+ *
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+ ******************************************************************************/
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+
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+#include "msp430.h"
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+#include "HAL_PMM.h"
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+
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+#define _HAL_PMM_DISABLE_SVML_
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+#define _HAL_PMM_DISABLE_SVSL_
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+#define _HAL_PMM_DISABLE_FULL_PERFORMANCE_
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+
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+#ifdef _HAL_PMM_DISABLE_SVML_
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+#define _HAL_PMM_SVMLE  SVMLE
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+#else
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+#define _HAL_PMM_SVMLE  0
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+#endif
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+
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+#ifdef _HAL_PMM_DISABLE_SVSL_
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+#define _HAL_PMM_SVSLE  SVSLE
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+#else
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+#define _HAL_PMM_SVSLE  0
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+#endif
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+
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+#ifdef _HAL_PMM_DISABLE_FULL_PERFORMANCE_
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+#define _HAL_PMM_SVSFP  SVSLFP
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+#define _HAL_PMM_SVMFP  SVMLFP
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+#else
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+#define _HAL_PMM_SVSFP  0
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+#define _HAL_PMM_SVMFP  0
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+#endif
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+
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+/*******************************************************************************
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+ * \brief   Increase Vcore by one level
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+ *
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+ * \param level     Level to which Vcore needs to be increased
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+ * \return status   Success/failure
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+ ******************************************************************************/
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+static unsigned int SetVCoreUp(unsigned char level)
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+{
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+  unsigned int PMMRIE_backup, SVSMHCTL_backup, SVSMLCTL_backup;
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+
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+  // The code flow for increasing the Vcore has been altered to work around
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+  // the erratum FLASH37.
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+  // Please refer to the Errata sheet to know if a specific device is affected
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+  // DO NOT ALTER THIS FUNCTION
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+
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+  // Open PMM registers for write access
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+  PMMCTL0_H = 0xA5;
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+
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+  // Disable dedicated Interrupts
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+  // Backup all registers
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+  PMMRIE_backup = PMMRIE;
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+  PMMRIE &= ~(SVMHVLRPE | SVSHPE | SVMLVLRPE | SVSLPE | SVMHVLRIE |
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+        SVMHIE | SVSMHDLYIE | SVMLVLRIE | SVMLIE | SVSMLDLYIE );
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+  SVSMHCTL_backup = SVSMHCTL;
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+  SVSMLCTL_backup = SVSMLCTL;
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+
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+  // Clear flags
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+  PMMIFG = 0;
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+
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+  // Set SVM highside to new level and check if a VCore increase is possible
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+  SVSMHCTL = SVMHE | SVSHE | (SVSMHRRL0 * level);
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+
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+  // Wait until SVM highside is settled
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+  while ((PMMIFG & SVSMHDLYIFG) == 0);
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+
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+  // Clear flag
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+  PMMIFG &= ~SVSMHDLYIFG;
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+
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+  // Check if a VCore increase is possible
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+  if ((PMMIFG & SVMHIFG) == SVMHIFG) {      // -> Vcc is too low for a Vcore increase
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+  	// recover the previous settings
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+  	PMMIFG &= ~SVSMHDLYIFG;
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+  	SVSMHCTL = SVSMHCTL_backup;
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+
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+  	// Wait until SVM highside is settled
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+  	while ((PMMIFG & SVSMHDLYIFG) == 0);
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+
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+  	// Clear all Flags
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+  	PMMIFG &= ~(SVMHVLRIFG | SVMHIFG | SVSMHDLYIFG | SVMLVLRIFG | SVMLIFG | SVSMLDLYIFG);
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+
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+  	PMMRIE = PMMRIE_backup;                 // Restore PMM interrupt enable register
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+  	PMMCTL0_H = 0x00;                       // Lock PMM registers for write access
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+  	return PMM_STATUS_ERROR;                // return: voltage not set
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+  }
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+
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+  // Set also SVS highside to new level
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+  // Vcc is high enough for a Vcore increase
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+  SVSMHCTL |= (SVSHRVL0 * level);
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+
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+  // Wait until SVM highside is settled
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+  while ((PMMIFG & SVSMHDLYIFG) == 0);
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+
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+  // Clear flag
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+  PMMIFG &= ~SVSMHDLYIFG;
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+
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+  // Set VCore to new level
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+  PMMCTL0_L = PMMCOREV0 * level;
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+
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+  // Set SVM, SVS low side to new level
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+  SVSMLCTL = SVMLE | (SVSMLRRL0 * level) | SVSLE | (SVSLRVL0 * level);
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+
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+  // Wait until SVM, SVS low side is settled
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+  while ((PMMIFG & SVSMLDLYIFG) == 0);
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+
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+  // Clear flag
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+  PMMIFG &= ~SVSMLDLYIFG;
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+  // SVS, SVM core and high side are now set to protect for the new core level
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+
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+  // Restore Low side settings
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+  // Clear all other bits _except_ level settings
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+  SVSMLCTL &= (SVSLRVL0+SVSLRVL1+SVSMLRRL0+SVSMLRRL1+SVSMLRRL2);
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+
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+  // Clear level settings in the backup register,keep all other bits
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+  SVSMLCTL_backup &= ~(SVSLRVL0+SVSLRVL1+SVSMLRRL0+SVSMLRRL1+SVSMLRRL2);
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+
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+  // Restore low-side SVS monitor settings
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+  SVSMLCTL |= SVSMLCTL_backup;
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+
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+  // Restore High side settings
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+  // Clear all other bits except level settings
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+  SVSMHCTL &= (SVSHRVL0+SVSHRVL1+SVSMHRRL0+SVSMHRRL1+SVSMHRRL2);
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+
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+  // Clear level settings in the backup register,keep all other bits
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+  SVSMHCTL_backup &= ~(SVSHRVL0+SVSHRVL1+SVSMHRRL0+SVSMHRRL1+SVSMHRRL2);
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+
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+  // Restore backup
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+  SVSMHCTL |= SVSMHCTL_backup;
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+
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+  // Wait until high side, low side settled
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+  while (((PMMIFG & SVSMLDLYIFG) == 0) && ((PMMIFG & SVSMHDLYIFG) == 0));
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+
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+  // Clear all Flags
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+  PMMIFG &= ~(SVMHVLRIFG | SVMHIFG | SVSMHDLYIFG | SVMLVLRIFG | SVMLIFG | SVSMLDLYIFG);
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+
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+  PMMRIE = PMMRIE_backup;                   // Restore PMM interrupt enable register
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+  PMMCTL0_H = 0x00;                         // Lock PMM registers for write access
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+
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+  return PMM_STATUS_OK;
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+}
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+
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+/*******************************************************************************
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+ * \brief  Decrease Vcore by one level
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+ *
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+ * \param  level    Level to which Vcore needs to be decreased
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+ * \return status   Success/failure
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+ ******************************************************************************/
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+static unsigned int SetVCoreDown(unsigned char level)
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+{
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+  unsigned int PMMRIE_backup, SVSMHCTL_backup, SVSMLCTL_backup;
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+
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+  // The code flow for decreasing the Vcore has been altered to work around
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+  // the erratum FLASH37.
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+  // Please refer to the Errata sheet to know if a specific device is affected
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+  // DO NOT ALTER THIS FUNCTION
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+
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+  // Open PMM registers for write access
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+  PMMCTL0_H = 0xA5;
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+
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+  // Disable dedicated Interrupts
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+  // Backup all registers
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+  PMMRIE_backup = PMMRIE;
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+  PMMRIE &= ~(SVMHVLRPE | SVSHPE | SVMLVLRPE | SVSLPE | SVMHVLRIE |
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+        SVMHIE | SVSMHDLYIE | SVMLVLRIE | SVMLIE | SVSMLDLYIE );
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+  SVSMHCTL_backup = SVSMHCTL;
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+  SVSMLCTL_backup = SVSMLCTL;
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+
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+  // Clear flags
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+  PMMIFG &= ~(SVMHIFG | SVSMHDLYIFG | SVMLIFG | SVSMLDLYIFG);
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+
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+  // Set SVM, SVS high & low side to new settings in normal mode
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+  SVSMHCTL = SVMHE | (SVSMHRRL0 * level) | SVSHE | (SVSHRVL0 * level);
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+  SVSMLCTL = SVMLE | (SVSMLRRL0 * level) | SVSLE | (SVSLRVL0 * level);
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+
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+  // Wait until SVM high side and SVM low side is settled
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+  while ((PMMIFG & SVSMHDLYIFG) == 0 || (PMMIFG & SVSMLDLYIFG) == 0);
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+
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+  // Clear flags
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+  PMMIFG &= ~(SVSMHDLYIFG + SVSMLDLYIFG);
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+  // SVS, SVM core and high side are now set to protect for the new core level
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+
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+  // Set VCore to new level
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+  PMMCTL0_L = PMMCOREV0 * level;
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+
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+  // Restore Low side settings
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+  // Clear all other bits _except_ level settings
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+  SVSMLCTL &= (SVSLRVL0+SVSLRVL1+SVSMLRRL0+SVSMLRRL1+SVSMLRRL2);
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+
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+  // Clear level settings in the backup register,keep all other bits
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+  SVSMLCTL_backup &= ~(SVSLRVL0+SVSLRVL1+SVSMLRRL0+SVSMLRRL1+SVSMLRRL2);
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+
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+  // Restore low-side SVS monitor settings
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+  SVSMLCTL |= SVSMLCTL_backup;
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+
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+  // Restore High side settings
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+  // Clear all other bits except level settings
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+  SVSMHCTL &= (SVSHRVL0+SVSHRVL1+SVSMHRRL0+SVSMHRRL1+SVSMHRRL2);
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+
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+  // Clear level settings in the backup register, keep all other bits
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+  SVSMHCTL_backup &= ~(SVSHRVL0+SVSHRVL1+SVSMHRRL0+SVSMHRRL1+SVSMHRRL2);
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+
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+  // Restore backup
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+  SVSMHCTL |= SVSMHCTL_backup;
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+
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+  // Wait until high side, low side settled
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+  while (((PMMIFG & SVSMLDLYIFG) == 0) && ((PMMIFG & SVSMHDLYIFG) == 0));
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+
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+  // Clear all Flags
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+  PMMIFG &= ~(SVMHVLRIFG | SVMHIFG | SVSMHDLYIFG | SVMLVLRIFG | SVMLIFG | SVSMLDLYIFG);
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+
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+  PMMRIE = PMMRIE_backup;                   // Restore PMM interrupt enable register
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+  PMMCTL0_H = 0x00;                         // Lock PMM registers for write access
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+  return PMM_STATUS_OK;		                // Return: OK
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+}
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+
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+unsigned int SetVCore(unsigned char level)
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+{
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+  unsigned int actlevel;
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+  unsigned int status;
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+
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+  status = 0;
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+  level &= PMMCOREV_3;                       // Set Mask for Max. level
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+  actlevel = (PMMCTL0 & PMMCOREV_3);         // Get actual VCore
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+                                             // step by step increase or decrease
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+  while (((level != actlevel) && (status == 0)) || (level < actlevel)) {
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+    if (level > actlevel) {
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+      status = SetVCoreUp(++actlevel);
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+    }
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+    else {
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+      status = SetVCoreDown(--actlevel);
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+    }
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+  }
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+
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+  return status;
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+}